[1]

S. Sharma and B. Kaur, “Performance investigation of Asymmetric Double Gate Doping Less Tunnel FET with Si/Ge heterojunction,” IET Circuits, Devices Syst., vol. 14, no. 5, pp. 695-701,  2020, doi: 10.1049/iet-cds.2019.0290.

[2]

S. Sharma, R. Basu, and B. Kaur, “Interface trap charges associated reliability analysis of Si/Ge heterojunction doping less TFET” IET Circuits, Devices Syst., 2021, doi: 10.1049/cds2.12037.

[3]

S. Sharma, R. Basu, B. Kaur, “Insights into temperature influence on Analog/RF and linearity performance of a Si/Ge heterojunction Asymmetric Double gate doping less TFET,” Appl. Phys. A 127, 392 (2021). https://doi.org/10.1007/s00339-021-04541-6

[4]

Baljit Kaur, Arvind Sharma, Naushad Alam, S.K. Manhas, Bulusu Anand,”A variation aware timing model for a 2-input NAND gate and its use in sub-65nm CMOS standard cell characterization,” Microelectronics Journal, Volume 53, 2016, Pages 45-55, ISSN 0026-2692, https://doi.org/10.1016/j.mejo.2016.03.010.

[5]

B. Kaur, N. Alam, S. K. Manhas and B. Anand, "Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 12, pp. 3407-3415, Dec. 2014, doi: 10.1109/TCSI.2014.2336511.

[6]

Mishra, A.K., D., V., Pal, Y. and Kaur, B. (2021), "Design and mathematical analysis of a 7T SRAM cell with enhanced read SNM using PMOS as an access transistor", Circuit World, Vol. ahead-of-print No. ahead-of-print. https://doi.org/10.1108/CW-05-2020-0095.

[7]

Baljit Kaur, “Hardware reduction technique by using two-dimensional radon transform,” Int. Journal of Advanced Computer Engineering and Architecture (IJACEA), vol. 2, no. 2, pp. 223-230, Jun. Dec. 2012.

[8]

Baljit Kaur and Manoj Kumar Majumder, “A modified parallel pipeline projection engine architecture for two-dimensional radon transform computation,” International Journal of Computational Intelligence and Telecommunication Systems (serials publications), vol. 2, no. 2, pp. 69-78, 2011, ISSN: 2229-3078.

[9]

Baljit Kaur, “Synthesis of low power sequential circuits,” Int. Journal of Recent Trends in Engg., vol. 2, no. 5, Nov. 2009, ISSN: 1797-9617, available at: http://www.academypublisher.com/ijrte/vol02/no05/ijrte0205232233.pdf.

[10]

Baljit Kaur, “Performance comparison between LMS and NLMS algorithm,” Indian Journal of Applied Research, vol. 1, no. 6, pp. 63-65, Mar. 2011, ISSN: 2249-555X, online available at: http://ijar.in/march/20.pdf.

[1]

Alok Kumar Mishra, Shubham Sinha, Subbarao D.D.V, D. Vaithiyanathan and Baljit Kaur, “Study and Implementation of Low Power Decoder using DVL and TGL Logic”, Proc. IEEE Madras Section International Conference (MASCON 2021), Chennai, India, August 27 – 28, 2021.

[2]

Alok Kumar Mishra, Shubham Sinha, Subbarao D.D.V, D. Vaithiyanathan and Baljit Kaur, “Implementation and Investigation of Different SRAM Cells using DLTFET Device”, Proc. IEEE Madras Section International Conference (MASCON 2021), Chennai, India, August 27 – 28, 2021.

[3]

D. Vaithiyanathan, Alok Kumar Mishra, Twinkle Bhardwaj, Vipul Jee Verma, Baljit Kaur, “Power Consumption and Delay Comparison of a Modified TCFF with Existing FF Implemented using FinFET and Load Test Circuit Analysis”, Proc. IEEE Madras Section International Conference (MASCON 2021), Chennai, India, August 27 – 28, 2021.

[4]

S. Kumar, S. Sharma and B. Kaur, “Leakage Power Estimation for ISCAS C17 Benchmark Circuit,” 2019 6th International Conference on Computing for Sustainable Global Development (INDIACom), New Delhi, India, 2019, pp. 108-112.

[5]

S. Bharti, S. Sharma, A. Verma, M. Bharti, and B. Kaur, “Performance analysis of Pocket Doped Junction-Less TFET,” 2020 International Symposium on Devices, Circuits and Systems(ISDCS),Howrah, India, 2020, pp. 1-4, doi: 10.1109/ISDCS49393.2020.9263024.

[6]

A. Verma, S. Sharma, S. Bharti, M. Bharti, and B. Kaur, “Design of Tunnel Junction Engineered Dopingless TFET for Low power Applications,” 2020 International Symposium on Devices, Circuits and Systems (ISDCS), Howrah, India, 2020, pp. 1-6, doi: 10.1109/ISDCS49393.2020.9262986

[7]

S. Sharma, S. Kumar, A. K. Mishra, D. Vaithiyanathan and B. Kaur, “PVT Aware Analysis of ISCAS C17 Benchmark Circuit” In: Singari R.M., Mathiyazhagan K., Kumar H. (eds) Advances in Manufacturing and Industrial Engineering. Lecture Notes in Mechanical Engineering. Springer, Singapore, 2020. https://doi.org/10.1007/978-981-15-8542-5_107

[8]

S. Sharma, R. Basu, and B. Kaur, “Performance evaluation of a novel Si0.6Ge0.4/Ge dopingless TFET for enhanced low power analog/RF applications” in Proc. 3rd International Conference on VLSI, Communication and Signal processing (VCAS 2020), Motilal Nehru National Institute of Technology (MNNIT Allahabad), October 9-11, 2020, India.

[9]

H. Nath, S. Sharma, A. Verma, and B. Kaur “Comparative analysis of a Dopingless Tunnel FET and MOSFET based Current Mirror” in Proc. 3rd International Conference on VLSI, Communication and Signal processing (VCAS 2020), Motilal Nehru National Institute of Technology (MNNIT Allahabad), October 9-11, 2020, India.

[10]

H. Nath, S. Sharma, A. Verma, and B. Kaur “A Dopingless Tunnel FET and MOSFET based comparative study of a Simple Current Mirror” in Proc. 2020 1st International Conference on Energy, Materials Sciences and Mechanical Engineering (EMSME), National Institute of Technology Delhi, Delhi, India, October 30 - November 1, 2020.

[11]

S. Sharma, R. Basu, and B. Kaur, "DC and linearity performance of a novel Si0.6Ge0.4/Ge Dopingless Tunnel FET for ultra-low voltage applications," 2021 International Symposium on Devices, Circuits and Systems (ISDCS), 2021, pp. 1-5, doi: 10.1109/ISDCS52006.2021.9397899.

[12]

S. Sharma, R. Basu, and B. Kaur, "Performance Investigation of a Si/Ge Heterojunction Asymmetric Double Gate DLTFET Considering Temperature and ITC Variations," 2021 22nd International Symposium on Quality Electronic Design (ISQED), 2021, pp. 314-314, doi: 10.1109/ISQED51717.2021.9424354.

[13]

S. Sharma, R. Basu, and B. Kaur, “Temperature associated reliability analysis of a Si/Ge Heterojunction Dopingless Tunnel FET considering Interface Trap Charges," 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 198-203, doi: 10.1109/DevIC50843.2021.9455866.

[14]

Raghav Chawla, Sarita Yadav, Arvind Sharma, Baljit Kaur, Rajendra Pratap, and Bulusu Anand,”TSV Induced Stress Model and Its Application in Delay Estimation” accepted for publication in Proc. IEEE  S3S conference, San Fransisco, California, USA, Oct. 15-18, 2018.

[15]

Yogesh Chaurasiya, Surabhi Bhargava, Arvind Sharma, Baljit Kaur, and Bulusu Anand, "Timing Model for Two Stage Buffer and Its Application in ECSM Characterization", in Proc. IEEE  19th International Symposium  on VLSI Design and Test (VDAT 2015), Ahmadabad, Gujrat, India,  pp. 1-6, Jun. 26-29, 2015, DOI: 10.1109/ISVDAT.2015.7208075.

[16]

Sandeep Miryala, Baljit Kaur, B. Anand, and S. K. Manhas, “Efficient Nanoscale VLSI Standard Cell Library Characterization Using a Novel Delay Model,” in Proc. IEEE 12th International Symposium on Quality Electronic Design 2011 (ISQED 2011), Santa Clara, CA, USA, pp. 458-463, Mar. 14-16, 2011, DOI: 10.1109/ISQED.2011.5770767

[17]

Baljit Kaur, Sandeep V., B. Anand, and S. K. Manhas, “An Accurate Current Source Model for CMOS Based Combinational Logic Cell,” in Proc. IEEE 13th International Symposium on Quality Electronic Design 2012 (ISQED 2012), Santa Clara, CA, USA, pp. 561-565, Mar. 19-21, 2012, DOI:  10.1109/ISQED.2012.6187549.

[18]

Surabhi Singh, Baljit Kaur, B. K. Kaushik, and S. Dasgupta, “Leakage Current Reduction Using Modified Gate Replacement Technique for CMOS VLSI Circuit,” International Conference on Communications, Devices and Intelligent Systems (CODIS2012), Jadavpur University, Kolkata, pp. 464-467, Dec. 28-29, 2012, DOI: 10.1109/CODIS.2012.6422239

[19]

Baljit Kaur, Sandeep Miryala, B. Anand, and S. K. Manhas, “An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies,” 14h IEEE International Symposium on Quality Electronic Design 2013 (ISQED 2013), Santa Clara, CA, USA, pp. 458-463, Mar. 4-6, 2013.

[20]

Baljit Kaur and Manoj Kumar Majumder, “Novel VLSI architecture for two-dimensional radon transform computations,” in Proc. IEEE 1st International Conference on Recent Advances in Information Technology (RAIT 2012), Dhanbad, pp. 570-575, Mar. 15-17, 2012, DOI: 10.1109/RAIT.2012.6194591.

[21]

Baljit Kaur and Manoj Kumar Majumder, “Modified PPPE architecture for two-dimensional radon transform computation,” in Proc. IEEE International Conference on Image Information Processing (ICIIP 2011), Shimla, pp. 1-6, Nov. 3-5, 2011, DOI: 10.1109/ICIIP.2011.6108844.

[1]

S. Bharti, S. Sharma, A. Verma, M. Bharti, and B. Kaur, “Analog/RF and DC Performance Enhancement of a Pocket-Doped Junction-Less TFET for Low Power Application. In: Mallick P.K., Meher P., Majumder A., Das S.K. (eds) Electronic Systems and Intelligent Computing. Lecture Notes in Electrical Engineering, vol 686. Springer, Singapore, 2020. https://doi.org/10.1007/978-981-15-7031-5_28

[2]

A. Verma, S. Sharma, S. Bharti, M. Bharti, and B. Kaur, “Design and Investigation of Tunnel Junction Engineered Dopingless-TFET with Improved DC and RF/Analog Parameters Analysis. In: Mallick P.K., Meher P., Majumder A., Das S.K. (eds) Electronic Systems and Intelligent Computing. Lecture Notes in Electrical Engineering, vol 686. Springer, Singapore, 2020. https://doi.org/10.1007/978-981-15-7031-5_32

[3]

V. Kumar, S. Sharma, and B. Kaur, “A Novel Design of Fast and Low Power Pull-Up and Pull-Down Voltage Level Shifter. In: Mallick P.K., Meher P., Majumder A., Das S.K. (eds) Electronic Systems and Intelligent Computing. Lecture Notes in Electrical Engineering, vol 686. Springer, Singapore, 2020,  https://doi.org/10.1007/978-981-15-7031-5_35

[4]

Baljit Kaur, “VLSI architecture based on two-dimensional radon transform computation,” Advances in Engineering Research, Vol. 7, Nova Science Publishers, Inc., New York, USA, 2013.